1 . Field of the Invention
The present invention relates to a phase-locked loop circuit, and more particularly, to a phase-locked loop circuit with a partial digitalized structure for suppressing excess leakage current and simultaneously improving the performance of the phase-locked loop circuit.
2 . Description of the Prior Art
A phase-locked loop (PLL) circuit is a common electronic circuit using a feedback scheme to simultaneously reference instant phases of both a reference signal and a feedback signal, thereby outputting a required clock signal. When a phase relation between two different clock signals stays within a required fixed range, the PLL circuit at this time is in a “phase locked” status.
Please refer to FIG. 1. FIG. 1 is a block diagram illustrating a conventional PLL circuit 100. The conventional PLL circuit 100 includes a detecting circuit 120 (e.g., a phase/frequency detector, PFD), a charge pump 130, a low pass filter 140, and an oscillator 150 (e.g., a voltage controlled oscillator, VCO); moreover, a PLL circuit (e.g., the PLL circuit 100) may further include a first frequency divider 110 (having a frequency-dividing factor expressed as N) and/or a second frequency divider 160 (having a frequency-dividing factor expressed as M).
The first frequency divider 110 will divide a reference signal Fref to make a frequency of the frequency-divided reference signal Fref-div generated from the first frequency divider 110 be 1/N times that of the reference signal Fref. Simultaneously, the output signal Fout is fed back to the second frequency divider 160, and the second frequency divider 160 divides a frequency of the output signal Fout to generate the frequency-divided feedback signal Ffb-div that has a frequency equal to 1/M times that of the output signal Fout.
As shown in FIG. 1, the detecting circuit 120 detects a phase relation between the frequency-divided reference signal Fref-div and a frequency-divided feedback signal Ffb-div to thereby output a detecting signal indicative of a phase leading condition or phase lagging condition between two inputs of the detecting circuit 120. Therefore, the outputted detecting signal is selectively an up signal UP or a down signal DN, depending upon the phase comparison result.
The charge pump 130 and the low pass filter 140 are used to generate a control signal (e.g., a voltage signal Vctr) as an input signal of the oscillator 150 according to the detecting signal (i.e., the up signal UP or the down signal DN); in this way, the oscillator 150 is then capable of generating the output signal Fout with a specific frequency according to magnitude of the control signal Vctr. The frequency of the output signal Fout is equal to
            F      ref        *          M      N        ,where Fref represents the frequency of the input reference signal Fref, and M and N represent frequency-dividing factors mentioned above.
That is, in a PLL circuit 100, the oscillator 150 generates an output signal Fout with a specific frequency in response to a control signal (e.g., Vctr). If the control signal (e.g., Vctrl) has poor signal quality and fails to keep at a required voltage level, the incorrect control signal Vctrl would lead to the improper output signal Fout.
Because of the charge pump 130, the low pass filter 140 and the oscillator 150 employed in the conventional PLL circuit 100 however, are commonly implemented using analog circuits. If the frequency-dividing factor N is large (i.e., 1/N is small ) and/or if the reference signal Fref has low frequency, the detecting circuit 120 will hence compare the two input signals, i.e., Fref-div and Ffb-div, in a long period, resulting in an unstable control signal Vctrl. This degrades performance of the conventional PLL circuit 100.
FIG. 2 is a block diagram illustrating partial structure of the PLL circuit 100 shown in FIG. 1. As shown in FIG. 2, the low pass filter 140 is implemented using a resistor 142 and two capacitors 144 and 146. The conventional analog structures of the low pass filter 140 and the charge pump 130 will make the voltage V1 be extremely affected by the leakage current via the resistor 142 and the capacitors 144 and 146 and hence make the voltage signal Vctrl difficult to maintain at the demanded voltage. This causes the conventional oscillator 150 to generate an incorrect output signal Fout, and degrades performance of the PLL circuit 100. In other words, the resultant frequency of the output signal Fout is probably not equal to the desired frequency
      F    ref    *            M      N        .  
In view of at least these issues mentioned above, it becomes clear that there remains considerable room for improvement of conventional PLL circuits.